Many People Have been wondering How will, Sony be able to Offer a powerful chipset in the PS4 ,and a Powerful but yet make it for the consumer with a price friendly "affordable price" and make the system Powerful and robust at low cost to the consumer. Many think there will be a trade off. Well yes and No. there is a way to do it and that is 3D stacked TSV chipset's. Its one of the way's and there is more reason to believe in fact its a Most likely is the direction that Sony is taking with the design of the chipset in the next Playstation Living room console.
1st. lets look at the recent Head of design for Playstation systems and what he stated early Last Jan!
Masaaki Tsuruta, CTO of Sony Computer Entertainment Masaaki Tsuruta, CTO of Sony Computer Entertainment, says that the company is working on a system-on-chip (SoC) to underpin the product for "seven to 10 years".
The PlayStation 3 will be at least seven years old by the time its successor arrives, but is generally considered to have lasted longer than was originally expected.
A firm launch for the fourth generation console - not to be called PlayStation 4 - was pushed out again late last year.
Its designed-in longevity is largely a matter of economics.
The Cell Broadband Engine that powered the PS3 cost $400m to develop;
"the main SoC for the incoming console is likely to be a 3D stack incorporating thru-silicon-via technology and could be the first $1bn hardware design project."
http://mandetech.com/2012...aki-tsuruta-interview/
So right there the Head CTO states the Most likely choice is 3D Stacked TSV, why would he say that, well there is very good reason.
What is Sony doing with SCE system chipset's right now?
here is what type of chip's they are making right now for their Game systems
Sony’s PS Vita Uses Chip-on-Chip SiP – 3D, but not 3D
Posted on
July 5, 2012 by
Chipworks Inside we found the usual set of wireless chips, motion sensors, and memory, but the key to the increased performance of the PS Vita is the Sony CXD5315GG processor, a quad- core ARM Cortex-A9 device with an embedded Imagination SGX543MP4+ quad-core GPU. Above I said that we found memory, but actually the only discrete memory that we found on the motherboard was 4 GB of Toshiba flash; and Sony’s specification states that there is 512 MB (4 Gb) regular RAM, plus 128 MB (1 Gb) VRAM (video RAM). In a phone that would tell me that there is memory in a package-on-package (PoP) configuration, mobile SDRAM in the top part and the processor in the bottom part.
However, when we took the part off the board and did a set of x-rays, the side view proved me wrong – it’s a stack, and the close-up shows that there appear to be five dies in there, a thick die at the base, a thinner one immediately on top and three smaller die on top of that. The second die down could be a spacer, since there don’t seem to bond wires going to it.
"This immediately led us to speculate – if the second die up is the VRAM, is it wide I/O DRAM, and is it using through-silicon vias (TSVs)? Time for a real cross-section to check that out, and almost predictably we were disappointed:"
This type of face-to-face connection showed up back in 2006 in the original Sony PSP, and Toshiba had dubbed it “semi-embedded DRAM”, now they are calling it “
Stacked Chip SoC”. The ball pitch is an impressive ~45 µm, almost as tight as
TI’s copper pillars, but they are staggered to achieve 40-µm pitch. So what are the five chips that are in the stack? At the base we have the processor chip; face to face with it is a Samsung 1-Gb wide I/O SDRAM; and the top three dies comprise two Samsung 2-Gb mobile DDR2 SDRAMs, separated by a spacer die, and conventionally wire-bonded. The base die is ~250 µm thick, and the others ~100 – 120 µm. When we look at the die photos of the processor and the 1-Gb memory, we can see that they are purposely laid out for the stacked-chip configuration, since in the centres of both is an array of matching bond pads.
Close examination reveals that there are 1080 pads in two blocks of 540 (2 sub-blocks of 45 rows of 6 pads), so likely 2 x 512 bit I/O operation, possibly sub-divided into 4 x 128.
So why would Sony do this?
"
Last year at ISSCC Samsung described a similar wide I/O DRAM using TSVs [1], claiming a data bandwidth of 12.8 Gb/s, four times the bandwidth of an equivalent LPDDR2 part. I doubt that the authors expected their design to be in a volume consumer device before the end of the year, but that seems to be what happened!"
By combining the processor with the different memories in the same package in the Vita, Sony and Toshiba have produced one of the few true system-in-package (SiP) parts that we have seen. And I would call it 3D, even though industry convention is now restricting that term to TSV-based parts – so it’s not 3D, in our current argot.
http://www.chipworks.com/...hip-sip-3d-but-not-3d/
Next Part The Development From the Cell to what the PS4 chip can be designed forward.
